1. Field of the Invention
The present invention relates to a semiconductor memory device. More particularly, it relates to a bipolar-transistor type semiconductor memory device having a redundancy circuit portion for replacing a defective circuit portion such as a defective memory cell existing in a regular memory cell array.
2. Description of the Related Art
Generally, a conventional semiconductor memory device having a redudancy circuit portion for replacing a defective circuit portion such as a defective memory cell comprises an address buffer and decoder, a regular decoder and driver, a regular memory cell array, a comparison and switching circuit, a programmable read only memory (PROM), a redundancy decoder and driver, and a redundancy memory cell array. If a defective memory cell is detected by carrying out the test for the regular memory cell array during the production process of the memory device, all address bit signals (for example, row address bit signals) constructing the address data corresponding to the defective memory cell are preliminarily programmed in the PROM.
Thus, when predetermined address bit signals (in this case, row address bit signals) are input to the address buffer and decoder in order to carry out a write operation or read operation, the input address bit signals are compared with the above programmed address bit signals in order to detect whether or not each logic of the corresponding address bit signal coincides, by using the comparison and switching circuit. If, as a result of the above comparison, it is detected that at least one logic of the input address bit signals does not coincide with that of the corresponding programmed address bit signal, the regular decoder and driver carries out the decoding operation in accordance with the input row address bit signals supplied through the address buffer and decoder, and as a result, a predetermined word line is selected in accordance with the input row address bit signals from a plurality of word lines arranged in the regular memory cell array through the regular decoder and driver.
Conversely, if it is detected that each logic of the input address bit signals coincides with that of the corresponding programmed address bit signal, the comparison and switching circuit outputs the control signal so as to inhibit the decoding operation of the regular decoder and driver and to enter the redundancy decoder and driver into an active state. As a result, a redundancy word line arranged in the redundancy memory cell array is selected through the redundancy decoder and driver, instead of the predetermined word line corresponding to the input row address bit signals arranged in the regular memory cell array.
However, in the above conventional memory device, it is possible to select only one redundancy word line, instead of one word line to which the defective memory cell is connected, by providing the PROM in which all address bit signals constructing the row address data corresponding to the above defective memory cell are programmed. Therefore if it is desired to increase the number of the redundancy word lines in order to prevent the selection of each of several word lines to which a number of defective memory cells are connected, it is necessary to increase the number of the PROMs. In the PROMs, all address bit signals constructing a plurality of row address data corresponding to the defective memory cells are programmed, and the number of the comparison circuits for comparing each logic of the input address bit signal with that of the corresponding programmed address bit signal. Thus, a problem arises in that the total capacity of the device is increased, and accordingly, the entire structure of the increased comparison circuits also becomes large, particularly when the number of the address bit signals constructing each address data is increased. Further the number of the redundancy word lines or redundancy bit lines to be selected instead of the regular word lines or regular bit lines to which the defective memory cells are connected is increased.